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? freescale semiconductor, inc., 2005. all rights reserved. freescale semiconductor technical data freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. mc145170-2/d rev. 5, 1/2005 mc145170-2 scale 2:1 package information d suffix plastic dip package case 751b package information dt suffix tssop package case 948c package information p suffix sog package case 648 ordering information device operating temperature range package mc145170p2 t a = -40 to 85c plastic dip mc145170d2 sog-16 MC145170DT2 tssop-16 1 introduction the new mc145170-2 is pin-for- pin compatible with the mc145170-1. a comparison of the two parts is shown in table 1 on page 2 . the mc145170-2 is recommended for new designs and has a mo re robust power-on reset (por) circuit that is more responsive to momentary power supply interruptions. th e two devices are actually the same chip with mask opti ons for the por circuit. the more robust por circuit draws approximately 20 a additional supply current. note that the maximum specification of 100 a quiescent supply current has not changed. the mc145170-2 is a single-chip synthesizer capable of direct usage in the mf, hf, and vhf bands. a special architecture makes this p ll easy to program. either a bit- or byte-oriented format may be used. due to the patented bitgrabber ? registers, no addr ess/steering bits are required for random access of the three registers. thus, tuning can be accomp lished via a 2-byte serial transfer to the 16-bit n register. mc145170-2 pll frequency synthesizer with serial interface contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 electrical characteristics . . . . . . . . . . . . . . . 3 3 pin connections . . . . . . . . . . . . . . . . . . . . . . . 9 4 design considerations . . . . . . . . . . . . . . . . 18 5 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
mc145170-2 technical data, rev. 5 2 freescale semiconductor introduction the device features fully programmable r and n counters, an amplifier at the f in pin, on-chip support of an external crystal, a programmable reference out put, and both single- and dou ble-ended phase detectors with linear transfer functions (no d ead zones). a configuration (c) register allows the part to be configured to meet various applications. a pate nted feature allows the c register to shut off unused outputs, thereby minimizing noise and interference. in order to reduce lock times and prevent erroneous da ta from being loaded into the counters, a patented jam-load feature is included. whenev er a new divide ratio is loaded in to the n register, both the n and r counters are jam-loaded with th eir respective values and begin counting down together. the phase detectors are also initialized during the jam load. ? operating voltage range: 2.7 to 5.5 v ? maximum operating frequency: ?_ _???)_ ??? _???)? ?)5)??? ?)_)???? )?_)?_? _)_)??_ (??_ ?_?5 ??5___ ? ?????5?? ??_??) ?) ??_??(? ??_??(? ?) ?)_ ?_? ??? ?5 ( ( (
electrical characteristics mc145170-2 technical data, rev. 5 freescale semiconductor 3 figure 1. block diagram 2 electrical characteristics table 2. maximum ratings (voltages referenced to v ss ) parameter symbol value unit dc supply voltage v dd -0.5 to 5.5 v dc input voltage v in -0.5 to v dd + 0.5 v dc output voltage v out -0.5 to v dd + 0.5 v dc input current, per pin i in ?? ?? ? ?? (5_?_? ? ?? ?5? ?) ) ) ?) ) bitgrabber r register 15 bits lock detector and control bitgrabber c register 8 bits phase/frequency detector a and control por phase/frequency detector b and control bitgrabber n register 16 bits osc shift register and control logic enb osc in d in clk osc out f in 1 2 7 5 4 3 15 16 16 ld pd out f r f v 10 15 14 13 11 9 pin 16 = v dd pin 12 = v ss input amp 6 4-stage reference divider ref out 3 dout 8 f v control f r f v 15-stage r counter f r control 16-stage n counter this device contains 4,800 active transistors.
mc145170-2 technical data, rev. 5 4 freescale semiconductor electrical characteristics table 3. electrical characteristics (voltages referenced to v ss , t a = -40 to 85 ( ?)_)_ ( ? ? ?) ?)_ _)_ ?)_? ?)_ ?)5_ ( ? ? ?) ?)_ _)_ ?)?5 )?_ )_ ? ?) _)_ ?)?_ ?)?? ( ? ?? ?) _)_ ?)? ?)? ( ? (?? ?) _)_ ?)5 _)? ( ? ?) ?)? ?)_ ?) ?)_ _)_ ?)?? ?)5 ?)5 ( ? ?)? ?)? _)? ?) ?)_ _)_ (?)?? (?)5 (?)5 ( ?)? ?)_ ?)5 ( ?)? ?)_ (?)5 ? _)_ ?)? _)_ ?_? ( _)_ _)_ ??? _)? _)_ ??? _?? ?)??)? ? ( ? ?) (() ) ?) )??)5? ?)_???)_)? )?_?_)?_))
electrical characteristics mc145170-2 technical data, rev. 5 freescale semiconductor 5 table 4. ac interface characteristics ( t a = -40 to 85c, c l = 50 pf, input t r = t f = 10 ns, unless otherwise noted.) parameter symbol figure no. v dd v guaranteed limit unit serial data clock frequency (note: refer to clock t w below) f clk 2 2.7 4.5 5.5 dc to 3.0 dc to 4.0 dc to 4.0 mhz maximum propagation delay, clk to d out t plh , t phl 2 , 6 2.7 4.5 5.5 150 85 85 ns maximum disable time, d out active to high impedance t plz , t phz 3 , 7 2.7 4.5 5.5 300 200 200 ns access time, d out high impedance to active t pzl , t pzh 3 , 7 2.7 4.5 5.5 0 to 200 0 to 100 0 to 100 ns maximum output transition time, d out _? ? 5 ?) ?)_ _)_ ?_? _? _? ??? ? 5 ?) ?)_ _)_ ?? ?_? ?_? ( ( ?? ( ( ?? _) (??_ ??) ) ? ?) ?)_ _)_ __ ?? ?? ?? _ ?) ?)_ _)_ ?_ ??? ??? ( ? _ ?) ?)_ _)_ ??? ?? ?? ? ?) ?)_ _)_ ?55 ??_ ??_ ? ?) ?)_ _)_ ??? ??? ???
mc145170-2 technical data, rev. 5 6 freescale semiconductor electrical characteristics 2.1 switching waveforms 10% v dd v ss 1/fclk d out clk 90% 50% 90% 50% 10% t plh t phl t tlh t thl t w t w t f t r enb d out d out 50% v dd v ss 50% t pzh t pzl t plz 50% t phz 10% 90% v dd v ss high impedance high impedance figure 2. figure 3. d in clk 50% valid 50% t su t h v dd v ss v dd v ss clk enb 50% t su t h first clk last clk t rec 50% v dd v ss v dd v ss t w(h) figure 4. figure 5. * includes all probe and fixture capacitance. test point device under test cl* test point device under test cl* *includes all probe and fixture capacitance. 7.5 k ? connect to v dd when testing t plz and t pzl . connect to v ss when testing t phz and t pzh . figure 6. test circuit figure 7. test circuit
electrical characteristics mc145170-2 technical data, rev. 5 freescale semiconductor 7 figure 8. test circuit, f in table 6. loop specifications (t a = -40 to 85c) parameter test condition symbol figure no. v dd v guaranteed range unit min max input frequency, f in [note] v in _?? ?)? ?) )? ?)_ _)_ _)? _)? ?_ ?_ ? ??? ?_ ?_ ( ?)? ? ?) )? ?)_ _)_ ?)? ?)? ?)? ?)? ?? ?_ ? _ ? ? ? ? ?? ?) )? ?)_ _)_ ?)? ?)? ?)? ?)? ?? ?? ?_ ?_ ? ?? ?? ?) ?)_ _)_ ( ?? ?? ?) ?)_ _)_ ( ?)? ?)? _? ? ?? ?) ?)_ _)_ ( ?? ?5 ( ??? ? ? _? ? ?? ?) ?)_ _)_ ( ( ( ( 5_ 5? ( ( ( ( ( ( )? )? () ?_ ?? ) sine wave generator 100 pf mc145170-2 test point v+ v dd f in f v v in 50 ? * v ss *characteristic impedance
mc145170-2 technical data, rev. 5 8 freescale semiconductor electrical characteristics figure 9. test circuit, osc circuitry externally driven [note] figure 10. circuit to eliminate self-oscillation, osc circuitry externally driven [note] note use the circuit of figure 10 to eliminate self-oscillation of the osc in pin when the mc145170-2 has power applied with no external signal applied at v in . (self-oscillation is not harm ful to the mc145170-2 and does not damage the ic.) c1 test point v dd ref out v ss osc in osc out c2 v+ mc145170-2 50% refout 1/f ref out figure 12. test circuit figure 11. test circuit, osc circuit with crystal 10% 90% output t tlh t thl 50% t w test point device under test cl* *includes all probe and fixture capacitance. output figure 14. test load circuit figure 13. switching waveform sine wave generator 50 ? 0.01 f test point v dd osc in f r v in v+ v ss mc145170-2 osc out 5.0 m ? sine wave generator 50 ? 0.01 f test point v dd osc in f r v in v+ v ss mc145170-2 osc out v+ 1.0 m ? no connect 1.0 m ?
pin connections mc145170-2 technical data, rev. 5 freescale semiconductor 9 3 pin connections 3.1 digital interface pins d in _ ? (( )? ??5 ? ?? ) ?_( ) ?_ )? ) ) ) )) ) ?)_)_) ?_ ?5 ? ? ) _? ) (() ?????_??( ??? ? ) ( ) ? (( (( )??5(???( ) ) ) ) ?_?? ?_ ?5 ? ? ) ? ? ) ) ???? ? ?5 ?_?? ? ? ?_ ? ? ? 5_) ) )? ?_???) ) )? ?????) ) )?
mc145170-2 technical data, rev. 5 10 freescale semiconductor pin connections clk typically switches near 50% of v dd and has a schmitt-trigge red input buffer. slow clk rise and fall times are allowed. see the last paragraph of d in for more information. note to guarantee proper operati on of the power-on reset (por) circuit, the clk pin must be held at the potential of either the v ss or v dd pin during power up. that is, the clk input should not be floated or toggled while the v dd pin is ramping from 0 to at least 2.7 v. if control of the clk pin is not practical during power up, the in itialization sequence shown in figure 15 must be used. enb (5 ?) ? ( ) ? )(( ? ) ) ) ) ( _? ) ) ( ? ?5(???( ( () ) ?( ) ? ? ) () ) )? ? ??? () (
pin connections mc145170-2 technical data, rev. 5 freescale semiconductor 11 from each pin to ground (up to a maximum of 30 pf each, including stray capacitance). an external feedback resistor of 1.0 to 5.0 m ? ) ?? ) _ ? ( ?? ) )) ) ) ? 5 loop specifications table on page 7 . these maximum frequencies apply for r counter divide ra tios as indicated in the table. for very small ratios, the maximum frequency is limited to the divide ratio times 2 mhz. (reason: the phase/frequency dete ctors are limited to a maximu m input frequency of 2 mhz.) if an external source is available which swings virtua lly rail-to-rail (v dd to v ss ), then dc coupling can be used. in the dc-coupled case, no external feedback resistor is needed. osc out must be a no connect to avoid loading an internal node on the device, as noted above. for frequencies below 1 mhz, dc coupling must be used. the r counter is a static c ounter and may be opera ted down to dc. however, wave shaping by a cmos buffer may be required to ensure fast rise and fall times into the osc in pin. see figure 25 . each rising edge on the osc in pin causes the r counter to decrement by one. ref out ? ( ) ?5 ) ) ((( (() ?? loop specifications table. therefore, divide values for the reference divider are restri cted to two or higher for osc in frequencies above 10 mhz. if unused, the pin should be floated and should be disabled via th e c register to mi nimize dynamic power consumption and electroma gnetic interference (emi). 3.3 counter output pins f r ? ?_() ?) ) ) ? ) _ ?5 ) ? ? ) ?) ?)
mc145170-2 technical data, rev. 5 12 freescale semiconductor pin connections when activated, the f r signal appears as normally low and pulse s high. the pulse width is 4.5 cycles of the osc in pin signal, except when a divide ratio of 1 is selected. when 1 is selected, the osc in signal is buffered and appears at the f r pin. f v ?? ?5() ?) ) ) ? ) ??5___ ) ?) ?) ) )? ? ) ( ) ( ?? ( )??? ?_ ) 5 ) ?) ? ?) ? ) 5 ?) ) ) ?_ ) ?) (? ? ( () ? ) ? ) ? ? ) ?? ?5
pin connections mc145170-2 technical data, rev. 5 freescale semiconductor 13 frequency of f v < f r or phase of f v lagging f r : positive pulses from high impedance frequency and phase of f v = f r : essentially high-impedan ce state; voltage at pin determined by loop filter pol bit (c7) = high frequency of f v > f r or phase of f v leading f r : positive pulses from high impedance frequency of f v < f r or phase of f v lagging f r : negative pulses from high impedance frequency and phase of f v = f r : essentially high-impedan ce state; voltage at pin determined by loop filter this output can be enabled, disabled, and i nverted via the c register. if desired, pd out can be forced to the high-impedance state by utilizati on of the disable feature in the c register (patented). (? ???_ ) ? ) ? ) ? ? ) ?? ?5 ? ? ?) ?? ( ) ? ) ?)( ) )
mc145170-2 technical data, rev. 5 14 freescale semiconductor pin connections 3.5 power supply v dd ?5 ?)_)_ ) (? ) ?) ) ?? ) ) ?_) (( ) )?? ) ?)?? ?) (( ?)?) enb clk d in power up 123 4 or more clocks 5 1234 don't cares don't cares one zeroes zero
pin connections mc145170-2 technical data, rev. 5 freescale semiconductor 15 figure 16. c register access and format (8 clock cycles are used) enb clk d in msb lsb c7 c6 c5 c4 c3 c2 c1 c0 1 234 5678 * * at this point, the new byte is transferred to the c register and stored. no other registers are affected. c7 - pol: select the output polarity of the phase/fre quency detectors. when set high, this bit inverts pd out and interchanges the ? ) ) ) 5(? ? ) ? ? ) ? ? () ) _( ) ) ) ?(??(? ) ?) ?( ) )) ?( ) )) ? ? ? ? ? ? ??? ??? ?? ??? ?? ??? ? ??? ??5 ??? ? ??? ??5
mc145170-2 technical data, rev. 5 16 freescale semiconductor pin connections figure 17. r register access and formats (either 24 or 15 clock cycles can be used)
pin connections mc145170-2 technical data, rev. 5 freescale semiconductor 17 figure 18. n register access and format (16 clock cycles are used) figure 19. phase/frequency detector and lock detector output waveforms enb clk d in 12345678 msb lsb n10n9n8n7n6n5n4n3n2n1n0 n11 n12 n13 n14 n15 9 10111213141516 0 0 0 0 0 0 0 0 0 0 0 f f 0 0 0 0 2 2 2 2 2 2 2 f f 0 1 2 3 5 6 7 8 9 a b e f not allowed not allowed not allowed not allowed not allowed not allowed not allowed n counter = 40 n counter = 41 n counter = 42 n counter = 43 n counter = 65,534 n counter = 65,535 hexadecimal value 0 0 0 0 0 0 0 0 0 0 0 f f decimal equivalent * . . . . . . . . .. .. . . . . . . . . .. .. * at this point, the two new bytes are transfe rred to the n register and stored. no ot her registers are affected. in addition, th e n and r counters are jam-loaded and begin counting down together. f r reference osc in r f v feedback (f in n pd out r v ld v h v l v h v h v h v l high impedance v h v l v l v l v h v l * v h = high voltage level v l = low voltage level *at this point, when both f r and f v are in phase, both the sinking and sourcing output fets are turned on for a very short internal. note: the pd out generates error pulses durin g out-of-lock conditions. w hen locked in phase and frequency, the output is high impedance and the voltage at that pin is determined by the low-pass filter capacitor. pdout, ? ?5 )
mc145170-2 technical data, rev. 5 18 freescale semiconductor design considerations 4 design considerations 4.1 crystal oscillator considerations the following options may be cons idered to provide a reference fr equency to our cmos frequency synthesizers. 4.1.1 use of a hybrid crystal oscillator commercially available temperature- compensated crystal oscillators (t cxos) or crystal- controlled data clock oscillators provide very stable reference frequencie s. an oscillator capable of cmos logic levels at the output may be direct or dc coupled to osc in . if the oscillator does not ha ve cmos logic levels on the outputs, capacitive or ac coupling to osc in may be used (see figures 9 and 10 ). for additional information about tcxos, visit www.freescale.com on the world wide web. 4.1.2 use of the on-chip oscillator circuitry the on-chip amplifier (a digital i nverter) along with an appropriate cr ystal may be used to provide a reference source frequency. a funda mental mode crystal, parallel resonant at the desired operating frequency, should be c onnected as shown in figure 20 . the crystal should be specified for a loading capacitance (c l ) which does not exceed 20 pf when used at the highest operating fr equencies listed in table 6 , loop specifications . larger c l values are possible for lower frequencies. assuming r1 = 0 ? ? _)? ?? 5)? ?? ?)? ?? ?? ?? ( ?) ? ) ) ? ) ?_?? )?)?? ( ) (((((((((((( ((((((((((((((( ( ? ? ? ? (((((((((((((((((((( ( ?
design considerations mc145170-2 technical data, rev. 5 freescale semiconductor 19 power is dissipated in the effective se ries resistance of the crystal, r e , in figure 22 . the maximum drive level specified by the crystal manufacturer represents the maximum stress that the crystal can withstand without damage or excessive shif t in operating frequency. r1 in figure 20 limits the drive level. the use of r1 is not necessary in most cases. to verify that the maximum dc supply voltage does not cause the crystal to be overdriven, monitor the output frequency at the ref out pin (osc out is not used because loading impacts the oscillator). the frequency should increase very slightly as the dc supply voltage is increas ed. an overdriven crystal decreases in frequency or become s unstable with an increase in supply voltage. the operating supply voltage must be reduced or r1 must be increased in value if the overdriven condition exists. the user should note that the oscillator start-up ti me is proportional to the value of r1. through the process of supplying crysta ls for use with cmos inverters, many crystal manufacturers have developed expertise in cm os oscillator design with crystals. di scussions with such manufacturers can prove very helpful. figure 20. pierce crystal oscillator circuit figure 21. parasitic capacitances of the amplifier and c stray figure 22. equivalent crystal networks r1* c2 c1 frequency synthesizer osc out osc in r f * may be needed in certain cases. see text. 5.0 to 10 pf c in c out c a osc in osc out c stray 2 1 2 1 2 1 rs ls cs re xe co note: values are supplied by crystal manufacturer (parallel resonant crystal).
mc145170-2 technical data, rev. 5 20 freescale semiconductor design considerations figure 23. phase-locked loop - low pass filter design c vco pd out r 1 c vco r 2 pd out r 1 a c r 2 c vco r v r 1 - + mc33077 or equivalent (note 3) r 1 r 2 (a) (b) (c) n k k vco nr 1 c ------------------------- = n n 2k k vco ---------------------------- - = fs () 1 r 1 sc 1 + ------------------------- - = n k k vco nc r 1 r 2 + () ------------------------------------ = 0.5 n r 2 c n k k vco ------------------------- + ?? ?? = fs () r 2 sc 1 + r 1 r 2 + () sc 1 + -------------------------------------------- - = n k k vco ncr 1 ------------------------- = n r 2 c 2 -------------------- = fs () r 2 sc 1 + r 1 sc ------------------------- - = notes: 1. for (c), r 1 is frequently split into two series re sistors; each resistor is equal to r 1 divided by 2. a capacitor c c is then placed from the midpoint to ground to furt her filter the error pulses. the value of c c should be such that the corner frequency of this network does not significantly affect ) ?) (() ) ??? ?(?? ?) ? ?_? ) () k vco vco gain () 2 ? f vco ? v vco -------------------------- =
design considerations mc145170-2 technical data, rev. 5 freescale semiconductor 21 figure 24. example application mcu threshold detector osc in v dd f in osc out v r v ss f r ld enb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vhf output buffer optional ref d in d out pd out v+ integrator vhf vco low-pass filter v+ optional loop error signals (note 1) m c 1 4 5 1 7 0 - 2 clk f v optional (note 5) (note 4) notes: 1. the ?) ( () (() ?) ?) ?( ) ) ? ) ) ) ?) (() _) )
mc145170-2 technical data, rev. 5 22 freescale semiconductor design considerations figure 25. low frequency operation using dc coupling note: the signals at points a and b may be low-frequency sinusoidal or square waves with slow edge rates or noisy signal edges. at points c and d, the signals are cleaned up, have sharp edge rates, and rail-to-rail signal swings. with signals as described at points c and d, the mc145170-2 is guaranteed to operat e down to a frequency as low as dc. no connect v+ v dd v ss osc in osc out f in a b c d mc145170-2
design considerations mc145170-2 technical data, rev. 5 freescale semiconductor 23 figure 26. input impedance at fin - series format (r + jx) (5.0 mhz to 185 mhz) figure 27. cascading two mc145170-2 devices 4 3 2 1 f in (pin 4) sog package marker frequency (mhz) resistance ( ? ? ? ? _ ?? (_?? _) ? ??? )? (? ?)_ ?_? ?_) (? ?)? ? ?_ ??)5 (?? ?) device #1 mc145170-2 cmos mcu optional d out enb clk d in device #2 mc145170-2 enb clk d in d out 33 k ? note 1 notes: 1. the 33 k ? ) () ?) ? ? ? )
mc145170-2 technical data, rev. 5 24 freescale semiconductor design considerations figure 28. accessing the c registers of two cascaded mc145170-2 devices figure 29. accessing the r registers of two cascaded mc145170-2 devices note: at this point, the new data is transferred to the c regist ers of both devices and stored. no other registers are affected . 1 2 7 8 9 1 0 1 5 1 6 1 7 1 8 2 3 2 4 2 5 2 6 3 1 3 2 3 3 3 4 3 9 4 0 c r e g i s t e r b i t s o f d e v i c e # 2 i n f i g u r e 2 7 c r e g i s t e r b i t s o f d e v i c e # 1 i n f i g u r e 2 7 x x x x x x c 7 c 6 c 0 x x x c 7 c 6 c 0 e n b c l k d i n n o t e note: at this point, the new data is transferred to the r regist ers of both devices and stored. no other registers are affected . e n b c l k d i n 1 2 8 9 1 0 2 5 2 6 2 7 3 0 3 1 3 9 4 0 4 1 4 2 4 4 4 5 r r e g i s t e r b i t s o f d e v i c e # 2 i n f i g u r e 2 7 r r e g i s t e r b i t s o f d e v i c e # 1 i n f i g u r e 2 7 x x x x r 1 4 r 1 3 x r 1 4 r 1 1 4 8 4 9 5 0 5 5 5 6 r 7 r 6 r 0 r 0 r 1 r 9 n o t e
mc145170-2 technical data, rev. 5 freescale semiconductor 25 design considerations figure 30. accessing the n registers of two cascaded mc145170-2 devices note: at this point, the new data is transferred to the n regist ers of both devices and stored. no other registers are affected . 1 2 8 9 1 0 1 5 1 6 1 7 2 3 2 4 2 5 3 1 3 2 3 3 n r e g i s t e r b i t s o f d e v i c e # 2 i n f i g u r e 2 7 n r e g i s t e r b i t s o f d e v i c e # 1 i n f i g u r e 2 7 x x x x x n 1 5 n 8 n 7 n 0 n 1 5 3 9 4 0 4 1 4 7 4 8 n 8 n 7 n 0 e n b c l k d i n n o t e
mc145170-2 technical data, rev. 5 26 freescale semiconductor design considerations figure 31. cascading two different device types v dd device #1 mc145170-2 cmos mcu optional d out enb clk d in device #2 note 2 enb clk d in output a (d out ) 33 k ? note 1 v pd v pd v cc v dd v+ notes: 1. the 33 k ? ) () ?) ? ? )
mc145170-2 technical data, rev. 5 freescale semiconductor 27 design considerations figure 32. accessing the c registers of two different device types figure 33. accessing the a and r registers of two different device types note: at this point, the new data is transferred to the c regist ers of both devices and stored. no other registers are affected . 1 2 7 8 9 1 0 1 5 1 6 1 7 1 8 2 3 2 4 2 5 2 6 3 1 3 2 3 3 3 4 3 9 4 0 c r e g i s t e r b i t s o f d e v i c e # 2 i n f i g u r e 3 1 c r e g i s t e r b i t s o f d e v i c e # 1 i n f i g u r e 3 1 x x x x x x c 7 c 6 c 0 x x x c 7 c 6 c 0 e n b c l k d i n n o t e note: at this point, the new data is transferred to the a regist er of device #2 and r register of device #1 and stored. no othe r registers are affected. e n b c l k d i n 1 2 1 6 1 7 1 8 2 0 2 1 2 2 3 0 3 1 3 2 3 9 4 0 4 1 4 2 4 3 a r e g i s t e r b i t s o f d e v i c e # 2 i n f i g u r e 3 1 r r e g i s t e r b i t s o f d e v i c e # 1 i n f i g u r e 3 1 x x a 2 3 a 2 2 a 1 9 a 1 8 a 0 x 4 6 4 7 4 8 5 5 5 6 r 9 r 8 r 0 a 8 r 1 4 r 1 3 a 9 n o t e
mc145170-2 technical data, rev. 5 28 freescale semiconductor design considerations figure 34. accessing the r and n registers of two different device types note: at this point, the new data is transferred to the r register of device #2 and n register of device #1 and stored. no othe r registers are affected. 1 2 8 9 1 0 1 5 1 6 1 7 2 3 2 4 2 5 3 1 3 2 3 3 r r e g i s t e r b i t s o f d e v i c e # 2 i n f i g u r e 3 1 n r e g i s t e r b i t s o f d e v i c e # 1 i n f i g u r e 3 1 x x x x x r 1 5 r 8 r 7 r 0 n 1 5 3 9 4 0 4 1 4 7 4 8 n 8 n 7 n 0 e n b c l k d i n n o t e
packaging mc145170-2 technical data, rev. 5 freescale semiconductor 29 5 packaging figure 35. outline dimensions for p suffix, dip-16 (case 648-08, issue r) figure 36. outline dimensions for d suffix, sog-16 (case 751b-05, issue k) -a- b f c s h g d 16 pl j l m seating plane 18 9 16 k -t- m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 010 010 s 0.020 0.040 0.51 1.01 _ _ _ _ notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. seating plane 0.49 16x b m 0.25 a t 0.35 1.75 1.35 0.25 0.10 6 t 16x 0.1 t 1.27 14x 7 1.25 0.40 0 0.25 0.19 section a-a notes: 1. dimensions are in millimeters. 2. dimensioning and tolerancing per asme y14.5m, 1994. 3. datums a and b to be determined at the plane where the bottom of the leads exit the plastic body. 4. this dimension does not include mold flash, protrusion or gate burrs, mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 5. this dimension does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm per side. this dimension is determined at the plane where the bottom of the leads exit the plastic body. 6. this dimension does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed 0.62 mm. 89 116 8x 6.2 5.8 m 0.25 b 4 10.0 9.8 a 4.0 3.8 b pin 1 index pin's number a a 5 0.50 x45 0.25
mc145170-2 technical data, rev. 5 30 freescale semiconductor packaging figure 37. outline dimensions for dt suffix, tssop-16 (case 948c-03, issue b) dim min max min max inches millimeters a --- 5.10 --- 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0047 d 0.05 0.25 0.002 0.010 f 0.45 0.55 0.018 0.022 g 0.65 bsc 0.026 bsc h 0.22 0.23 0.009 0.010 j 0.09 0.24 0.004 0.009 k 0.16 0.32 0.006 0.013 l 6.30 6.50 0.248 0.256 m 010 010 55 55 j1 0.09 0.18 0.004 0.007 k1 0.16 0.26 0.006 0.010 a b pin 1 identification l 18 9 16 16x ref k m 0.200 (0.008) t -p- d c seating g h m 0.100 (0.004) plane -t- -u- f m a a k k1 j j1 section a-a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimensions a and b are to be determined at datum plane -u-.
mc145170-2 technical data, rev. 5 freescale semiconductor 31 notes
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